v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
K {type=VOLTAGE_SOURCE
template="name=V? device=VOLTAGE_SOURCE footprint=none numslots=0 description=\\"dc power source\\" value=\\"DC 1V\\" "
tedax_format="footprint @name @footprint
value @name @value
device @name @device
@comptag"
format="@name @pinlist @value "

}
G {}
V {}
S {}
E {}
T {@name} 70 -65 2 1 0.333333 0.333333 {}
T {@value} 70 -45 2 1 0.333333 0.333333 {}


L 4 17.5 -62.5 42.5 -62.5 {}
L 4 17.5 -57.5 42.5 -57.5 {}

A 4 30 -60 30 0 360 {}





L 3 30 -120 30 -90 {}
B 5 27.5 -122.5 32.5 -117.5 {pinnumber=1
pinseq=1
name=+
dir=inout
}
T {@#0:pinnumber} 35 -100 2 1 0.266667 0.266667 {layer=13}
T {@#0:name} 30 -85 0 0 0.266667 0.266667 { hcenter=true}
L 3 30 -30 30 0 {}
B 5 27.5 -2.5 32.5 2.5 {pinnumber=2
pinseq=2
name=-
dir=inout
}
T {@#1:pinnumber} 35 -10 2 1 0.266667 0.266667 {layer=13}
T {@#1:name} 30 -35 2 1 0.266667 0.266667 { hcenter=true}
