v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=subcircuit
format="@name @pinlist @symname VTH=@VTH VHI=@VHI"
template="name=x1 VTH=1.5 VHI=3.0"
}
V {}
S {}
E {}
L 4 -70 -20 70 -20 {}
L 4 -70 40 70 40 {}
L 4 -70 -20 -70 40 {}
L 4 70 -20 70 40 {}
L 4 -90 -10 -70 -10 {}
L 4 70 -10 90 -10 {}
L 4 -90 10 -70 10 {}
L 4 -90 30 -70 30 {}
B 5 -92.5 -12.5 -87.5 -7.5 {name=D dir=in }
B 5 87.5 -12.5 92.5 -7.5 {name=Q dir=out }
B 5 -92.5 7.5 -87.5 12.5 {name=CK dir=in }
B 5 -92.5 27.5 -87.5 32.5 {name=VSS dir=in }
T {@symname} -31.5 -6 0 0 0.3 0.3 {}
T {@name} 75 -32 0 0 0.2 0.2 {}
T {D} -65 -14 0 0 0.2 0.2 {}
T {Q} 65 -14 0 1 0.2 0.2 {}
T {CK} -65 6 0 0 0.2 0.2 {}
T {VSS} -65 26 0 0 0.2 0.2 {}
