v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
K {type=spice-IO
template="device=spice-IO name=P? "
tedax_format="footprint @name @footprint
value @name @value
device @name @device
@comptag"
format="@name @pinlist @value "

}
G {}
V {}
S {}
E {}
T {@name} 65 -25 2 1 0.333333 0.333333 {}
T {.SUBCKT IO Pin} -1.2 -9.7 0 0 0.2 0.2 {}


L 4 20 -30 30 -40 {}
L 4 20 -30 30 -20 {}
L 4 30 -40 50 -40 {}
L 4 30 -20 50 -20 {}
L 4 50 -40 60 -30 {}
L 4 50 -20 60 -30 {}






L 3 0 -30 20 -30 {}
B 5 -2.5 -32.5 2.5 -27.5 {pinseq=1
pinnumber=1
dir=inout
name=1
}
